The present invention relates to a semiconductor device and method and apparatus for fabricating the same.
As the number of semiconductor devices integrated on a single chip has been steeply rising, the gap between adjacent interconnect layers has been drastically reduced, resulting in non-negligible increase in capacitance between these interconnect layers. In general, the larger a capacitance between interconnect layers, the lower the operating speed of a semiconductor device, because a line-to-line delay also increases accordingly. In order to prevent such decrease in the operating speed of semiconductor devices, various techniques of forming an interconnect layer with a low resistance using copper (Cu) have recently been suggested more and more often. Hereinafter, a conventional semiconductor device, including an interconnect layer of Cu., will be described with reference to FIGS. 25, 26, 27, 28, 29 and 30.
As shown in FIG. 30, this semiconductor device includes: a semiconductor substrate 1; a lower interconnect layer 2 formed on the surface of the semiconductor substrate 1; and a silicon dioxide (SiO2) film 3 formed over the semiconductor substrate 1 to cover the lower interconnect layer 2. A trisilicon tetranitride (Si3N4) film 4 is deposited over the SiO2 film 3, and another SiO2 film 5 is deposited on the Si3N4 film 4. An interlevel dielectric film is made up of the SiO2 film 3, Si3N4 film 4 and SiO2 film 5. In this interlevel di-electric film, a through hole 6, reaching the lower interconnect layer 2, and an interconnection channel or trench 7, communicating with the through hole 6, are formed. An upper interconnect layer 13, which is in electrical contact with the lower interconnect layer 2 via the through hole 6, is formed within the interconnection channel 7.
The upper interconnect layer 13 includes: a titanium (Ti) film 8 covering the inner side faces and bottom of the through hole 6 and interconnection channel 7; a titanium nitride (TiN) film 9 deposited on the Ti film 8; a Cu film 10 deposited on the TiN film 9; and a Cu film 11 deposited on the Cu film 10. Alternatively, the upper interconnect layer 13 may include a tantalum nitride (TaN) film instead of the TiN film 9.
Such a semiconductor device may be fabricated in the following manner.
First, as shown in FIG. 25, the lower interconnect layer 2 is formed on the semiconductor substrate 1. Next, as shown in FIG. 26, the SiO2 film 3, Si3N4 film 4 and SiO2 film 5 are deposited in this order and alternately subjected to photolithography and dry etching twice. In this manner, the through hole 6 is formed inside the SiO2 film 3 and Si3N4 film 4, and the interconnection channel 7 is formed inside the SiO2 film 5. Then, as shown in FIG. 27, the bottom of the through hole 6 is cleaned by dry etching. And the Ti film 8 and the TiN film 9 are deposited in this order by physical vapor deposition (PVD) and chemical vapor deposition (CVD) processes, respectively.
Next, as shown in FIG. 28, the surface of the TiN film 9 is exposed to N2 plasma, thereby increasing the density of the TiN film 9. As the case may be, this process step is sometimes omitted. Thereafter, as shown in FIG. 29, the Cu film 10 is deposited by a PVD process on the surface of the TiN film 9. However, the Cu film 10 is deposited only in the central region of the semiconductor substrate 1. The reason thereof will be described later.
After the surfaces of the TiN film 9 and Cu film 10 have been cleaned with sulfuric acid (H2SO4), the Cu film 11 is deposited on the surface of the Cu film 10 by an electroplating technique. Finally, respective portions of the Ti film 8, TiN film 9 and Cu films 10 and 11, which are deposited on the SiO2 film 5, are removed by a chemical/mechanical polishing (CMP) technique to complete the semiconductor device shown in FIG. 30.
The reason why the Cu film 10 is deposited only in the central region of the semiconductor substrate 1 will be described. Generally speaking, it is only in the central region of a semiconductor substrate that a metal layer can be removed by a CMP technique. Thus, part of the metal layer is ordinarily left in the peripheral region of the semiconductor substrate even after the polishing. If the Cu film is left in the peripheral region of the semiconductor substrate 1, then the Cu film is likely to peel off during a subsequent process step to contaminate an apparatus for fabricating the semiconductor device. Accordingly, a technique of preventing to a residue of a Cu film from being formed in the peripheral region of a semiconductor substrate 1 by depositing the Cu film only in the central region of the semiconductor substrate 1 is widely used.
If a semiconductor device is fabricated in this manner, however, the following problems are caused.
First, when a TaN film 9 is deposited by a CVD process, the connection resistance between the lower and upper interconnect layers 2 and 13 becomes high and the operating speed of the semiconductor device may decrease, because the resistivity of the TaN film 9 is high. It is probably because a large quantity of carbon (C) is contained in the TaN film 9 that the resistivity of the TaN film 9 is high.
Also, Cu atoms contained in the Cu films 10 and 11 reach the SiO2 films 3 and 5 through the TiN (or TaN) film 9. This is because the TiN (or TaN) film 9 cannot satisfactorily prevent the diffusion of the Cu atoms. The Cu atoms, which have reached the SiO2 films 3 and 5, are turned into mobile ions inside these films 3 and 5, thereby increasing the leakage current flowing between the through holes 6 and between adjacent portions of the upper interconnect layer 13. As a result, the semiconductor device is more likely to cause some failure during the operation thereof.
In addition, as shown in FIG. 29, when the Cu film 11 is deposited by an electroplating technique, a Cu film 12 is unintentionally deposited on the surface of the TiN film 9 adjacent to the Cu film 10. The adhesion of the Cu film 12 to the underlying TiN film 9 is poor. And the Cu film 12 easily peels off during the CMP process, thus considerably decreasing the yield of semiconductor devices.